1. Field of the Invention
This invention relates generally to an apparatus and method for delaying the output of an input data for a specified variable length of time. More particularly, this invention relates to an apparatus and method for delaying the output of an input data for a plurality of variable lengths of time with a delay circuit structure which allows simultaneous multiple input and multiple output operations thus increasing the throughput of a digital signal processor and meanwhile reduces the hardware requirements of the delay circuit.
2. Description of the Prior Art
As larger volume of data, often in the form of binary bits, are being electronically transmitted, stored and later retrieved, the precision and flexibility of controlling the delays for outputting an input item by a variable length of time often become very important design factors for various types of applications. The variable duration of delay time for outputting an input data item is usually measured in the unit of clock cycles of a data processor. For high bandwidth applications, not only that the clock rate of a data processor is required to be increased, but it is also required that the data processor is able to receive multiple input and generate multiple output simultaneously with different delay times which are precisely and flexibly adjustable. In addition to these increasing demands for system design to achieve high level of performance, another major criterion for integrated circuit (IC) implementation of the variable delay circuit is to maintain a simple and systematic circuit design. It is essential that the circuit for variable length delay may be conveniently implemented by the use of IC technology with circuit design which has less level of complexity such that the cost of design and manufacture of these delay circuits may be maintained at reasonable low levels.
Conventionally, for the purposes of synchronization or ghost cancellation, delays of blocks of video data are provided by the use of programmable shift registers. The delay circuit has a series of shift registers and the delay of the output is achieved by sequentially reading a data item into this series of shift registers and then sequentially reading it out. By repeating the input and output operations through this series of registers, a variable length of delay can be achieved. However, for the purpose of achieving extended variable delay, large number of shift registers with complex supporting control circuits would have to be employed and the delay circuit would become very big and expensive.
In order to overcome this limitation encountered by the shift-register type of delay circuits, several prior art variable length delay circuits are disclosed which employ a random access memory (RAM) to delay the output. Japanese Laying-open Gazette No. 38939/1978 entitled `Variable Length Shift Register Device` discloses a variable bit length shift register comprising a RAM to achieve the variable length delay. In another Japanese Laying-open Gazette No. 42529/1978 entitled `Variable Shift Register` discloses a variable bit length shift register comprising a RAM with a variable counter, and another Japanese Laying-open Gazette No. 42634/1978 entitled `Variable Shift Register` discloses a variable bit length shift register comprising a RAM and a ring counter for the purpose of delaying the output of an input data by a variable length. Since writing and reading operations can not be performed simultaneously on the RAM for the circuits disclosed in these three references, the techniques disclosed in these Japanese Applications are not suitable for modern applications. The limitation is caused by the difficulty that the length of one delay cycle must be at least twice the length of the access time to the RAM. Thus, the operation speed is limited. Additionally, as the writing cycles and the reading cycles must be controlled by different circuits, the control circuits becomes very complicate and may not be suitable for IC implementation.
Besides the above mentioned Japanese references, there are other RAM-based variable delay circuits well known in the art wherein reading and writing can be simultaneously performed. As all these RAM based variable delay devices employ multiple writing and reading operations to achieve the intended delays, depending on the number of input and output ports used, the following speed of input/output (I/O) operations are generally required in a delay circuit for time-sharing operations when the frequency of a system clock is X-Hz. A RAM-based delay circuit, when equipped with dual ports, may simultaneously read and write at a frequency of X-Hz to achieve the time-sharing application of this delay circuit to allow a minimum delay of (1/X) seconds. For a single-port system, in order to achieve a time-sharing operation, the I/O system must read and write at a frequency of 2X-Hz (double speed) for the purpose of delaying output with the same minimum duration of delay. In order to achieve a minimum length of delay of shorter duration, the I/O speed has to be proportionally increased. For example, for a minimum delay of (1/aX) seconds where a is an integer, the frequency of an I/O operation must be controlled at least 2(aX)-Hz for a system of single port and must be aX-Hz for a system with dual I/O ports. The system configuration for this type of implementation is to divide the RAM into separate and independent of a segments. Due to the need to write to and then read from the RAM, multiple input/output control circuits to manage the operations or writing and reading are required which greatly complicate the control circuits.
Nakabayashi et al. discloses in U.S. Pat. No. 4,876,670 entitled "Variable Delay Circuit for Delaying Input Data" (Issued on Oct. 24, 1989) a variable delay circuit for delaying the input data. The delay circuit has a two dimensional array of memory cells for storing the input data. A read address decoder and a write address decoder are used for generating a memory cell address to read and write the input data from and to selected memory cells. A programmable timing signal is generated by a time signal generator. The timing signal is generated to be synchronized with the operation of the writing of the input data in order to control the reading of the input data by the read address decoder after a programmable time delay. The programmable time delay can be set by the timing signal generator so that the time delay may be flexibly adjusted. The technique disclosed in this Patent may be more flexible for application to various time delaying devices, such circuits are however still limited by the highly sophisticate and complicate control circuits which must be implemented for the timing signal generator for generating programmable delay signals. The cost for design and manufacture of such circuits would prevent the delay circuits from being economically and broadly utilized. Additionally, the delay circuits as disclosed by Nakabayashi et al. is limited by the fact that it can generate a single delay output at a specific point in time. For high frequency applications, a demand for high bandwidth performance is also imposed on the variable delay circuits due to the single output limitation which further increases the cost in the implementation of the variable delay circuit.
Kawai et al. disclose in a U.S. Pat. No. 4,943,128, entitle `Variable Delay Circuit for Delaying Input Data` (Issued on Aug. 28, 1990) a variable delay circuit to delay the output of an input data. An address counter which counts the clock pluses sequentially to provide a count value as an address signal to a coincidence detecting circuit and a decoder. The coincidence detecting circuit receives a delay data generated by a delay data generating circuit. The coincidence detecting circuit then compares the delay data with the address signal and applies a reset signal to the address counter when the they coincident with each other. The address counter repeats the above operation sequentially in response to the reset signal after the count of address is reset to a predetermined value. The decoder specifies a memory for performing a reading and writing operation in response to the address signal. A control circuit is also used to control a data output circuit and a data input circuit to write and read the data from specific memory cells for storing the input data.
Even that the delay circuit as disclosed by Kawai et al. provides a greater degree of flexibility and control accuracy wherein the delayed output is generated by the coincidence detection circuit in cooperation with the address decoder, the delay circuit as disclosed by Kawai et al. suffers the same disadvantage as that encountered in the invention disclosed by Nakabayashi et al. The control circuits become even more complicate and difficult to design and manufacture. The delay circuits could cause the systems which use the disclosed devices to be more expensive to use. Furthermore, the delay circuit as disclosed by Kawai et al. suffers the same difficulty as that of Nabayashi as it also generates only one single delay output from one RAM at a time.
Since modern communication and multi-media systems often include various types of digital signal processing systems for performing video or audio signal processes. These systems commonly require very long yet dynamically changing delays. There exists an even greater demand to provide a delay circuit and design techniques which can handle these variable length delay requirements. It is desirable that these delay circuits are less complicate and meanwhile able to provide greater flexibility to generate multiple delayed output to satisfy the requirements of these modern digital signal processing systems.
The applicants of the present invention have submitted another co-pending patent application, assigned to the same assignee, to address these requirements. The disclosure made in that patent application (Patent Application number is yet to be assigned) is incorporated herein by reference. The invention as disclosed in that patent application is an attempt to overcome the limitation of the prior art by providing a less complicate delay circuit. One of the preferred embodiments, e.g., a delay circuit 5 is shown in FIGS. 1A and 1B wherein FIG. 1A is identical to FIG. 4 of the referenced Patent Application (Patent Application number is yet to be assigned). The delay circuit 5 employs only a single RAM 10 for supporting three tap banks. The single RAM 10 is controlled by a clock means 12 and provided with an access means 14, i.e., an I/O buffer, to perform the input and output functions. For the purpose of illustration, the RAM is assumed to be employed in a ghost cancellation system with a storage capacity of 512 storage locations. One of the key features realized by the referenced Patent Application (Patent Application number is yet to be assigned) is the fact that for a ghost cancellation system, the aggregate value of various delays commonly required is less then 512 which is the total lines of a video display on a television screen. Therefore, a complimentary relationship exists between various delay values and a plurality of these delays will not exceed 512 increments of delays in the aggregate. For that reason, the RAM 10 can be divided into three variable delay segments, i.e., segments 10-1, 10-2, and 10-3, as shown in Fig. 1B corresponding to the circuit functional block diagram as shown in FIG. 1A.
Referring to the description provided in the referenced Patent Application (Patent Application number is yet to be assigned) for FIG. 4, the RAM 10 is divided into three variable delay segments wherein each segment has a size of 150, 200, and 162 storage locations respectively. Three sets of circuitries implemented as `delay means`, i.e., delay means 16, 44, and 50 are used to control the writing of an input data and the reading of an output corresponding to a delayed input in segment 10-1, 10-2, and 10-3 respectively. Therefore, the delay circuit 5 as disclosed in this prior art patent application provides an improved variable delay circuit 5 which can accept requests for multiple delay values using only a single RAM with a single data input in each clock cycle via the I/O buffer 14. A single RAM can thus be used to provide the delayed output with different delays.
The variable delay circuit 5 as shown in FIGS. 1A and 1B is still limited by several difficulties. First of all, in order to generate three different delayed output items, the RAM has to be divided into three segments, i.e., segments 10-1, 10-2, and 10-3, and controlled by three delay means, i.e., the delay means 16, 44, and 50. These delay means 16, 44, and 50 cause the delay circuit 5 to occupy more IC chip surface areas and increases the complexity of the circuit design due to the interconnecting lines among these three set of delay means. This specific difficulty in requiring separate sets of delay control circuits to generate different delay output may often limit the number of delay requests to be less than three. Additional requests for different delay values would certainly add more circuits and cause the variable delay circuit to be too voluminous for fabrication as an IC circuit. Secondly, the length of each delay is limited by the fact that the aggregate of these three different delays must be less than the total locations of the RAM, e.g., 512. In case a first delay value requested is a long duration of delay, the second and the third delays may not be able to be processed simultaneously due to this limitation. Even that the delay circuit 5 as disclosed by this prior art patent application may be sufficient for the purpose of a ghost cancellation operation as of now, the usefulness of this variable delay circuit 5 may not be adequate for other types of application or even for newer techniques of ghost cancellation if greater ranges of delays or more dynamic variations of delays are required. Thirdly, in each clock cycle, the delay circuit 5 as shown can only read in a single input data and output a single delayed-input data through the I/O buffer 14. For modern high bandwidth applications, the requirements may become more demanding and dynamic such that a plurality of input data and output data are to be processed in each clock cycle. The delay circuit 5 would not be able to satisfy such requirements due to the reason that the I/O buffer 14 is operating at the speed of the system clock 12. Furthermore, in order to enable the processing of an additional delay request, another set of delay control circuits such as the delay means 16, 44, or 50 are to be added which would cause the delay circuit to become too complicate and voluminous for practical implementation.
Therefore, there is still a need in the art of variable length delay circuit to provide a circuit configuration and method such that the design and manufacture of such circuits can be simplified. Meanwhile, the circuit configuration and design method is required also to provide great degree of control flexibility and delay accuracy so that it can be suitable for various types of modern applications.